Power supply converter and method

ABSTRACT

A power supply converter and a method for adjusting a threshold voltage in the power supply converter. The circuit includes first and second switches having current conducting terminals commonly connected together to form a node. An energy storage element may be connected to the node and a zero current detection comparator may be connected to the node. A first voltage may be provided at the control terminal of the first switch that turns it off. After the first switch is off, determining whether the first switch turned off before or after the current in the energy storage element has reached zero. This may be accomplished by determining whether the voltage at the first node is positive or negative. If the voltage at the first node is negative, the threshold voltage is increased and if the voltage at the first node is positive the threshold voltage is decreased.

TECHNICAL FIELD

The present invention relates, in general, to power supplies and, moreparticularly, to switching mode power supplies.

BACKGROUND

Switching Mode Power Supplies (SMPS) are used in a variety of electronicdevices including laptop computers, cellular phones, personal digitalassistants, video games, video cameras, etc. They may convert a dcsignal at one voltage level to a dc signal at a different voltage level(this is a dc-dc converter), an Alternating Current (ac) signal to a dcsignal (this is a an ac-dc converter), a dc signal to an ac signal (thisis a dc-ac converter), or an ac signal to an ac signal (this is an ac-acconverter). Generally, switching mode power supplies transfer energyfrom an input node to an output node by means of a switch, an inductor,and control and feedback circuitry. One type of switching mode powersupply topology is a Buck converter in which the voltage appearing atthe output node is stepped down from the voltage appearing at the inputnode. A Buck converter may include a high side Field Effect Transistor(FET) and a low side FET, where the drain of the high side FET iscoupled for receiving an input signal, the source of the high side FETis commonly connected to the drain of a low side FET and to a terminalof an inductor, and the source of the low side FET is connected toground. The gates of the high and low side FETs are coupled forreceiving corresponding control signals. The other terminal of theinductor is connected to a load.

To optimize the efficiency of a converter such as, for example, a buckconverter, it is desirable to prevent a negative current from flowing inthe low side FET because the negative current increases conductionlosses from the FET which results in an increased power loss. Thus, aBuck converter is typically operated in a discontinuous operating modeto reduce conduction losses. In this operating mode the low side FET isturned off when the inductor current reaches zero. A drawback withturning off the low side FET is that if it is turned off before theinductor current reaches zero, current continues to flow through thebody diode of the low side FET which increases power losses. Conversely,if the low side FET is turned off too late, a negative inductor currentcauses current to flow through the body diode of the high side FET thatis off, which causes the converter circuit to ring thereby producingElectroMagnetic Interference (EMI).

Accordingly, it would be advantageous to have a method and circuit foradaptively adjusting the turn off of the low side FET in a switchingmode power supply. It would be of further advantage for the circuit andmethod to be cost efficient to implement.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood from a reading of thefollowing detailed description, taken in conjunction with theaccompanying drawing figures, in which like reference charactersdesignate like elements and in which:

FIG. 1 is a circuit schematic of a converter in accordance with anembodiment of the present invention;

FIG. 2 is a circuit schematic of a converter in accordance with anotherembodiment of the present invention;

FIG. 3 is a circuit schematic of a converter in accordance with anotherembodiment of the present invention;

FIG. 4 is a circuit schematic of a converter in accordance with anotherembodiment of the present invention;

FIG. 5 is a graph having plots that illustrate signals that aregenerated at various nodes in accordance with embodiments of the presentinvention; and

FIG. 6 is a graph having plots that illustrate signals that aregenerated at various nodes in accordance with embodiments of the presentinvention.

DETAILED DESCRIPTION

Generally, the present invention provides a circuit and a method foroperating a switching transistor in a discontinuous mode. In accordancewith embodiments of the present invention, a high side switchingtransistor has a drain coupled for receiving an input signal, a sourcecommonly connected to a drain of a low side switching transistor, to aninput of a comparator, and to an inductor to form a switch node. Thesource of the low side switching transistor is coupled for receiving asource of operating potential such as for example, operating potentialV_(SS). The other input of the comparator is coupled for receiving athreshold voltage and the other terminal of the inductor is coupled to aload. The switching transistors are coupled for receiving controlsignals from a switch drive module. The voltage at the switch node iscompared with the threshold voltage. If the voltage at the switch nodeis negative, there is a positive current flowing through the inductorand the zero current detector generates a control signal that raises thethreshold voltage so that the low side switching transistor turns offlater. If the voltage at the switch node is positive, there is anegative current flowing through the inductor and the zero currentdetector generates a control signal that decreases the threshold voltageso that the low side switching transistor turns on earlier. In otherwords, if the inductor current is negative, the low side switchingtransistor turns off too late, i.e., the low side switch opens too late,and if the inductor current is positive, the low side switchingtransistor turns off too early, i.e., the low side switch opens tooearly.

FIG. 1 is a schematic diagram of a converter 10 suitable for use with apower supply in accordance with an embodiment of the present invention.Converter 10 includes switches 12 and 14 coupled for receiving controlsignals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV), respectively, from adriver circuit 16. It should be noted that driver circuit 16 may also bereferred to as a switch drive module. More particularly, switches 12 and14 have control terminals connected to corresponding output terminals ofdriver circuit 16 for receiving high side drive signal V_(HS) _(—)_(DRV) and low side drive signal V_(LS) _(—) _(DRV), respectively.Switches 12 and 14 have current conducting terminals connected to eachother. In addition, switch 12 has a current conducting terminal coupledfor receiving an input voltage V_(IN) and switch 14 has a currentconducting terminal coupled for receiving a source of operatingpotential V_(SS). By way of example, source of operating potentialV_(SS) is at ground potential. An energy storage element 18 such as, forexample, an inductor, is coupled to the commonly connected currentconducting terminals of switches 12 and 14, which forms a node 20. Ancurrent I_(L18) flows through energy storage element 18. A diode 22 maybe coupled between node 20 and source of operating potential V_(SS). Aload 25 is coupled between an output terminal 23 of converter 10 andsource of operating potential V_(SS). An output voltage V_(OUT) appearsat output terminal 23.

Converter 10 includes a Zero Current Detection (ZCD) comparator 24having an inverting input terminal 46, a noninverting input terminal,and an output terminal. The noninverting input terminal of ZCDcomparator 24 is connected to node 20 for receiving a switching signalV_(SWN) that serves as a reference voltage for ZCD comparator 24,inverting input terminal 46 of ZCD comparator 24 is coupled forreceiving a signal V_(TH) that serves as an adjustable threshold signal,and the output terminal is connected to an input terminal of drivercircuit 16. By way of example, switching signal V_(SWN) and adjustablethreshold signal V_(TH) are voltage signals.

Converter 10 further includes a Zero Current Detection (ZCD) controlmodule 30 having a plurality of input terminals and at least one outputterminal. An output terminal 21 of control module 30 is connected toinverting input terminal 46 of ZCD comparator 24 for transmitting anadjustable threshold voltage V_(TH) to comparator 24. Input terminals 26and 28 of ZCD control module 30 and the noninverting input terminal ofZCD comparator 24 are connected to node 20. An input terminal 27 of ZCDcontrol module 30 is coupled for receiving a reference voltage V_(LSREF)and an input terminal 29 of ZCD control module 30 is coupled forreceiving a reference voltage V_(HSREF).

FIG. 2 is a schematic diagram of a converter 100 suitable for use with apower supply in accordance with another embodiment. What is shown inFIG. 2 is an embodiment of a ZCD control module 30A coupled to switches12 and 14, ZCD comparator 24, and driver circuit 16. It should be notedthat the ZCD control module has been identified by reference character30A in FIG. 2 to indicate that it may be configured differently from ZCDcontrol module 30 described with reference to FIG. 1. Thus, referencecharacter 30 has been preserved to identify ZCD control modules butreference character “A” has been appended to reference character 30 toindicate that the configurations of ZCD control modules 30 and 30A maybe the same or they may be different. Control module 30A comprisescomparators 32 and 34, where comparator 32 has a noninverting inputterminal connected to node 20 and an inverting input terminal connectedto reference voltage source V_(LSREF) and comparator 34 has an invertinginput terminal connected to node 20 and a noninverting input terminalconnected to reference voltage source V_(HSREF). Thus, the noninvertinginput terminal of comparator 32 and the inverting input terminal ofcomparator 34 serve as input terminals 26 and 28, respectively, of ZCDcontrol module 30 and the inverting terminal of comparator 32 and thenoninverting input terminal of comparator 34 serve as input terminals 27and 29, respectively, of ZCD control module 30. An output terminal ofcomparator 32 is connected to an input terminal of a three-input ANDgate 36 and an output terminal of comparator 34 is connected to an inputterminal of a three-input AND gate 38. A second input terminal of ANDgate 36 is connected to a second input terminal of AND gate 38, whichsecond input terminals are commonly connected together for receiving asignal VB_(LS) _(—) _(DRV) that serves as a control signal and a thirdinput terminal of AND gate 36 is connected to a third input terminal ofAND gate 38, which are commonly connected for receiving a signal VB_(HS)_(—) _(DRV) that serves as another control signal. Signal VB_(LS) _(—)_(DRV) indicates that low side switch 14 is off or open and signalVB_(HS) _(—) _(DRV) indicates that high side switch 14 is off or open.Signals VB_(HS) _(—) _(DRV) and VB_(LS) _(—) _(DRV) are complementarysignals to signals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV),respectively.

An output terminal of AND 36 is connected to an incrementing inputterminal of a counter 40 and an output terminal of AND gate 38 iscoupled to a decrementing input terminal of counter 40 through a timer42. It should be noted that timer 42 is an optional element and that theoutput terminal of AND gate 38 can be directly connected to thedecrementing input terminal of counter 40. An output terminal of counter40 is connected to an input terminal of a latch 44. The output terminalof latch 44 is connected to an inverting input terminal 46 of comparator24. Counter 40 and latch 44 have input terminals coupled for receiving apower on reset signal V_(POR). Latch 44 has a clocking input terminalcoupled to an output terminal of a three-input AND gate 48 which has aninput terminal coupled for receiving a high side drive signal V_(HS)_(—) _(DRV), an input terminal coupled for receiving a signal V_(SFT)_(—) _(OK), which indicates whether a soft start has completedcorrectly, and an input terminal coupled for receiving a signal V_(NO)_(—) _(FAULT) which indicates that no fault conditions have beendetected during start up or during operation. Examples of faultconditions include an over current event, an over voltage event,excessively high power dissipation, or the like. AND gates 36, 38, and48 may be referred to as logic gates.

FIG. 3 is a schematic diagram of a converter 150 suitable for use with apower supply in accordance with another embodiment. Converter 150 issimilar to converter 100 except that switches 12 and 14 have beenimplemented using n-channel field effect transistors 102 and 104. Fieldeffect transistors 102 and 104 have gate electrodes coupled forreceiving control signals from driver circuit 16. Field effecttransistor 102 has a drain electrode coupled for receiving input signalV_(IN) and a source electrode coupled to a drain electrode of fieldeffect transistor 104. The source electrode of field effect transistor104 is coupled for receiving source of operating potential V_(SS). Itshould be noted that the gate electrode of a field effect transistor maybe referred to as a control electrode and the source and drainelectrodes of a field effect transistor may be referred to as currentconducting electrodes.

FIG. 4 is a schematic diagram of a converter 200 suitable for use with apower supply in accordance with another embodiment. Converter 200includes ZCD comparator 24, comparators 32 and 34, driver circuit 16,field effect transistors 102 and 104, inductor 18, and diode 22. Likeconverters 10, 100, and 150, diode 22 is an optional element. It shouldbe noted that switches such as, for example, switches 12 and 14 may beused in place of switching transistors 102 and 104, respectively. Whatis shown in FIG. 4 is an embodiment of a ZCD control module 30B coupledto transistors 102 and 104, ZCD comparator 24, and driver circuit 16. Itshould be noted that the ZCD control module has been identified byreference character 30B in FIG. 4 to indicate that it may be configureddifferently from ZCD control module 30 described with reference toFIG. 1. Thus, reference character 30 has been preserved to identify ZCDcontrol modules but reference character “B” has been appended toreference character 30 to indicate that the configurations of ZCDcontrol modules 30 and 30B may be the same or they may be different.Control module 30B comprises comparators 32 and 34 where comparator 32has an output terminal connected to an input terminal of a three-inputAND gate 202 and comparator 34 has an output terminal connected to aninput terminal of a three-input AND gate 204. A delay element 206 has aninput terminal coupled for receiving a control signal HSLS_OFF and anoutput terminal commonly connected to a second input terminal of ANDgate 204 and to an input terminal of a delay element 208. Control signalHSLS_OFF indicates whether transistors 102 and 104 are on or off, i.e.,whether the switches are closed or open. Delay element 208 has an outputterminal connected to a second input terminal of three input AND gate202. An output terminal of AND gate 202 is connected to a clocking inputterminal of a flip-flop 210. In addition, flip-flop 210 has a set inputterminal coupled for receiving a source of operating potential such as,for example, V_(CC), an edge triggered data input terminal coupled forreceiving a Pulse Width Modulation (PWM) signal V_(PWM), and a dataoutput terminal connected to the incrementing input terminal of acounter 214. An output terminal of AND gate 204 is connected to aclocking input terminal of a flip-flop 212. In addition, flip-flop 212has a set input terminal coupled for receiving a source of operatingpotential such as, for example, V_(CC), an edge triggered data inputterminal coupled for receiving PWM signal V_(PWM), and a data outputterminal connected to the decrementing input terminal of counter 214.

Counter 214 has a set of n data input terminals coupled for receiving ann-bit input signal DATA, where n is an integer and a set of n outputterminals for transmitting an n-bit output signal to a Digital-to-AnalogConverter (DAC) 216. DAC 216 further includes a status input terminalcoupled to a status input terminal of counter 214 and coupled forreceiving a control signal PGOOD which indicates whether there has beena fault or soft start error during system startup. DAC 216 furtherincludes a clocking input terminal coupled to an output terminal of atwo input AND gate 218, where one of the input terminals of AND gate 218is coupled for receiving input signal PGOOD and the other input terminalis coupled for receiving a control signal HS_OFF, which indicateswhether transistor 102 is on or off.

Converter 200 further includes an operational amplifier 220 configuredas a summer. More particularly, operational amplifier 220 has aninverting input terminal, a noninverting input terminal, and an outputterminal, where the inverting input terminal is coupled to the outputterminal through a resistor 222. The output terminal of operationalamplifier 220 is also connected to inverting input terminal 46 of ZCDcomparator 24. The inverting input terminal of operational amplifier 220is coupled for receiving a threshold offset voltage V_(TH) _(—)_(OFFSET) through a resistor 224, and coupled to the output terminal ofDAC 216 through a resistor 226.

FIG. 5 is a timing diagram 250 illustrating electrical signals atvarious nodes of converters 10, 100, 150, and 200 (shown in FIGS. 1, 2,3, and 4, respectively) during their operation in accordance withembodiments of the present invention. More particularly, timing diagram250 illustrates voltage V_(HS) _(—) _(DRV) at the control terminal ofswitching transistor 102, voltage V_(LS) _(—) _(DRV) at the controlterminal of switching transistor 104, current I_(L18) flowing throughinductor 18, and voltage V_(SWN) at switching node 20 under a conditionin which switching voltage V_(SWN) is negative and inductor currentI_(L18) is positive. Under this condition, switching transistor 104turns off before inductor current I_(L18) reaches zero. Thus, it isdesirable to raise threshold voltage V_(TH) that appears at inputterminal 46 of ZCD comparator 24 so that switching transistor 104 turnsoff later, i.e., to delay switching transistor 104 turning off. Thus,converters 10, 100, 150, and 200 operate to increase the thresholdvoltage V_(TH) that appears at input terminal 46 of ZCD comparator 24.

Driver circuit 16 provides switching signals that turn on and turn offswitching transistors 102 and 104, i.e., close and open the switchingtransistors. It should be noted that in embodiments where switches suchas, for example switches 12 are used rather switching transistors 102and 104, respectively, driver circuit 16 provides switching signals thatclose and open switches 12 and 14. Preferably, driver circuit 16generates drive signals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV) suchthat they are not at a logic high voltage level at the same time therebyensuring that transistors 102 and 104 are not on at the same time, i.e.,the switches are not closed at the same time. This precludes thepossibility of input voltage V_(IN) being shorted to source of operatingpotential V_(SS), which is typically at ground potential. Optionally,driver circuit 16 can be configured to generate drive signals that arecomplementary signals to drive signals V_(HS) _(—) _(DRV) and V_(LS)_(—) _(DRV).

At time t₀, driver circuit 16 generates control signals V_(HS) _(—)_(DRV) and V_(LS) _(—) _(DRV) that change the operating states ofswitching transistors 102 and 104 by turning them off or turning themon. In this example, driver circuit has generated control signals thathave turned switching transistors 102 and 104 off at time t₀, i.e.,control signals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV) are at logiclow voltage levels. Inductor current I_(L18) is zero and switchingvoltage V_(SWN) is at a nominal level V_(SWN) _(—) _(NOM). Nominalvoltage level V_(SWN) _(—) _(NOM) is derived using a voltage dividerrelationship among switching transistors 102 and 104, input voltageV_(IN), and voltage V_(SS).

At time t₁ high side drive signal V_(HS) _(—) _(DRV) transitions from alogic low voltage level to a logic high voltage level while low sidedrive signal V_(LS) _(—) _(DRV) remains at a logic low voltage level. Inresponse to high side drive signal V_(HS) _(—) _(DRV) transitioning to alogic high voltage level and low side drive signal V_(LS) _(—) _(DRV)remaining at a logic low voltage level, voltage V_(SWN) at switchingnode 20 transitions to a voltage level V_(SWN) _(—) _(HL), which isgreater than reference voltages V_(LSREF) and V_(HSREF) and close to thevalue of input voltage V_(IN). A positive inductor current I_(L18) flowsfrom node 20 through inductor 18 and load 25.

At time t₂, driver circuit 16 generates a control signal that turns FET102 off and a control signal that leaves FET 104 off. In particular,gate voltage V_(HS) _(—) _(DRV) of switching transistor 102 transitionsto a logic low voltage level and gate voltage V_(LS) _(—) _(DRV) ofswitching transistor 104 remains at a logic low voltage level. Inresponse to the change in high side drive signal V_(HS) _(—) _(DRV) attime t₂, output voltage V_(OUT) decreases which results in switch nodevoltage V_(SWN) at node 20 decreasing to voltage level V_(SWN) _(—)_(LL) and inductor current I_(L18) beginning to decrease. Switch nodevoltage V_(SWN) is less than reference voltages V_(LSREF) and V_(LSREF),which leaves decrement signal V_(DEC) and increment signal V_(INC) thatare input into counter 214 and threshold voltage V_(TH) that appears atinput terminal 46 of comparator 24 unchanged.

At time t₃, low side drive signal V_(LS) _(—) _(DRV) transitions to alogic high voltage level turning on switching transistor 104, i.e.,closing the switch, which generates a drain-to-source on-voltage inswitching transistor 104 and causes switch node voltage V_(SWN) at node20 to increase to a voltage level V_(SWN) _(—) _(LH). Inductor currentI_(L18) continues to decrease.

At time t₄, high side drive signal V_(HS) _(—) _(DRV) remains at a logiclow voltage level and low side drive signal V_(LS) _(—) _(DRV)transitions from a logic high voltage level to a logic low voltagelevel. Low side drive signal V_(LS) _(—) _(DRV) being at a logic lowvoltage level turns off switching transistor 104 which causes switchnode voltage V_(SWN) at node 20 to decrease below voltage level V_(SWN)_(—) _(LH). This causes inductor current I_(L18) to decrease at a fasterrate as shown by the change in slope of the portion of the inductorcurrent plot between times t₄ and t₅ in FIG. 5.

At time t₅, inductor current I_(L18) reaches a zero value, i.e., currentI_(L18) stops flowing. Voltage V_(SWN) oscillates about its nominalvoltage V_(SWN) _(—) _(NOM) before settling to its nominal voltage.

After time t₅, signal V_(SWN) at node 20 and pulse width modulationsignal V_(PWM) causes flip-flops 210 and 212 to generate a decrementsignal that decrements counter 214 and adjusts threshold voltage V_(TH)so that switching transistor 104 turns off earlier and preferably whenswitching current I_(L18) reaches zero. In this example, althoughthreshold voltage V_(TH) appearing at input terminal 46 of ZCDcomparator 24 has been increased, it has not been increased sufficientlyso that inductor current I_(L18) is zero or substantially zero when lowside switching transistor 104 turns off. Thus, at time t₆ high sidedrive signal V_(HS) _(—) _(DRV) transitions from a logic low voltagelevel to a logic high voltage level while low side drive signal V_(LS)_(—) _(DRV) remains at a logic low voltage level. In response to highside drive signal V_(HS) _(—) _(DRV) transitioning to a logic highvoltage level and low side drive signal V_(LS) _(—) _(DRV) remaining ata logic low voltage level, switch node voltage V_(SWN) at switching node20 transitions to a voltage level V_(SWN) _(—) _(HF), which is greaterthan reference voltages V_(LSREF) and V_(HSREF) and close to the valueof input voltage V_(IN). A positive inductor current I_(L18) flows fromnode 20 through inductor 18 and load 25.

At time t₇, driver circuit 16 generates a control signal that turns FET102 off and a control signal that leaves FET 104 off. In particular,gate voltage V_(HS) _(—) _(DRV) of switching transistor 102 transitionsto a logic low voltage level and gate voltage V_(LS) _(—) _(DRV) ofswitching transistor 104 remains at a logic low voltage level. Inresponse to the change in high side drive signal V_(HS) _(—) _(DRV) attime t₇, output voltage V_(OUT) decreases which results in switch nodevoltage V_(SWN) at node 20 decreasing to voltage level V_(SWN) _(—)_(LL) and inductor current I_(L18) beginning to decrease. Switch nodevoltage V_(SWN) is less than reference voltages V_(HSREF) and V_(LSREF),which leaves decrement signal V_(DEC) and increment signal V_(INC) thatare input into counter 214 and threshold voltage V_(TH) that appears atinput terminal 46 of comparator 24 unchanged.

At time t₈, low side drive signal V_(LS) _(—) _(DRV) transitions to alogic high voltage level turning on switching transistor 104, i.e.,closing the switch, which generates a drain-to-source on-voltage inswitching transistor 104 and causes switch node voltage V_(SWN) at node20 to increase to a voltage level V_(SWN) _(—) _(LH). Inductor currentI_(L18) continues to decrease.

At time t₉, high side drive signal V_(HS) _(—) _(DRV) remains at a logiclow voltage level and low side drive signal V_(LS) _(—) _(DRV)transitions from a logic high voltage level to a logic low voltagelevel. Low side drive signal V_(LS) _(—) _(DRV) being at a logic lowvoltage level turns off switching transistor 104 which causes switchnode voltage V_(SWN) at node 20 to decrease below voltage level V_(SWN)_(—) _(LH). This causes inductor current I_(L18) to decrease at a fasterrate as shown by the change in slope of the portion of the inductorcurrent plot between times t₄ and t₅ in FIG. 5.

At time t₁₀, inductor current I_(L18) reaches a zero value, i.e.,current I_(L18) stops flowing. Voltage V_(SWN) oscillates about itsnominal voltage V_(SWN) _(—) _(NOM) before settling to its nominalvoltage.

This process continues, i.e., using signals V_(SWN) and V_(PWM) togenerate counter decrement signals, until threshold voltage V_(TH)appearing at input terminal 46 of comparator 24 is sufficientlyincreased so that low side switching transistor 104 turns off wheninductor current I_(L18) reaches zero or substantially zero.

FIG. 6 is a timing diagram 300 illustrating electrical signals atvarious nodes of converters 10, 100, 150, and 200 (shown in FIGS. 1, 2,3, and 4, respectively) during their operation in accordance withembodiments of the present invention. More particularly, timing diagram300 illustrates voltage V_(HS) _(—) _(DRV) at the control terminal ofswitching transistor 102, voltage V_(LS) _(—) _(DRV) at the controlterminal of switching transistor 104, current I_(L18) flowing throughinductor 18, and voltage V_(SWN) at switching node 20 under a conditionin which switching voltage V_(SWN) is positive, inductor current I_(L18)is negative, and switching transistor 104 turns off after inductorcurrent I_(L18) has reached zero. Thus, converters 10, 100, 150, and 200operate to decrease the threshold voltage V_(TH) that appears at inputterminal 46 of ZCD comparator 24 so that switching transistor 104 turnsoff earlier.

As discussed above, driver circuit 16 provides switching signals thatturn on and turn off switching transistors 102 and 104, i.e., close andopen the switching transistors. Preferably, driver circuit 16 generatesdrive signals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV) such that theyare not at a logic high level at the same time thereby ensuring thattransistors 102 and 104 are not on at the same time, i.e., the switchesare not closed at the same time. This precludes the possibility of inputvoltage V_(IN) being shorted to source of operating potential V_(SS),which is typically at ground potential. Although not shown, drivercircuit 16 can also generate drive signals that are complementarysignals to drive signals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV).

At time t₀, driver circuit 16 generates control signals V_(HS) _(—)_(DRV) and V_(LS) _(—) _(DRV) that change the operating states ofswitching transistors 102 and 104 by turning them off or turning themon. In this embodiment, driver circuit 16 has generated control signalsthat have turned switching transistors 102 and 104 off at time t₀, i.e.,control signals V_(HS) _(—) _(DRV) and V_(LS) _(—) _(DRV) are at logiclow voltage levels. Inductor current I_(L18) is zero and switchingvoltage V_(SWN) is at a nominal level V_(SWN) _(—) _(NOM). Nominalvoltage level V_(SWN) _(—) _(NOM) is derived using a voltage dividerrelationship among switching transistors 102 and 104, input voltageV_(IN), and voltage V_(SS).

At time t₁ high side drive signal V_(HS) _(—) _(DRV) transitions from alogic low voltage level to a logic high voltage level while low sidedrive signal V_(LS) _(—) _(DRV) remains at a logic low voltage level. Inresponse to high side drive signal V_(HS) _(—) _(DRV) transitioning to alogic high voltage level and low side drive signal V_(LS) _(—) _(DRV)remaining at a logic low voltage level, voltage V_(SWN) at switchingnode 20 transitions to a voltage level V_(SWN) _(—) _(HL), which isgreater than reference voltages V_(LSREF) and V_(HSREF) and close to thevalue of input voltage V_(IN). A positive inductor current I_(L18) flowsfrom node 20 through inductor 18 and load 25.

At time t₂, driver circuit 16 generates a control signal that turns FET102 off and a control signal that leaves FET 104 off. In particular,gate voltage V_(HS) _(—) _(DRV) of switching transistor 102 transitionsto a logic low voltage level and gate voltage V_(LS) _(—) _(DRV) ofswitching transistor 104 remains at a logic low voltage level. Inresponse to the change in high side drive signal V_(HS) _(—) _(DRV) attime t₂, output voltage V_(OUT) decreases which results in switch nodevoltage V_(SWN) at node 20 decreasing to voltage level V_(SWN) _(—)_(LL) and inductor current I_(L18) beginning to decrease. Switch nodevoltage V_(SWN) is less than reference voltages V_(HSREF) and V_(LSREF),which leaves decrement signal V_(DEC) and increment signal V_(INC) thatare input into counter 214 and threshold voltage V_(TH) that appears atinput terminal 46 of comparator 24 unchanged.

At time t₃, low side drive signal V_(LS) _(—) _(DRV) transitions to alogic high voltage level turning on switching transistor 104, i.e.,closing the switch, which generates a drain-to-source on-voltage inswitching transistor 104 and causes switch node voltage V_(SWN) at node20 to increase to a voltage level V_(SWN) _(—) _(LH). Inductor currentI_(L18) continues to decrease.

At time t₄, high side drive signal V_(HS) _(—) _(DRV) remains at a logiclow voltage level, low side drive signal _(VLS) _(—) _(DRV) remains at alogic high voltage level, and inductor current I_(L18) transitions tobecome a negative current.

At time t₅, high side drive signal V_(HS) _(—) _(DRV) remains at a logiclow voltage level and low side drive signal V_(LS) _(—) _(DRV)transitions from a logic high voltage level to a logic low voltagelevel. Low side drive signal V_(LS) _(—) _(DRV) being at a logic lowvoltage level turns off switching transistor 104 which causes switchnode voltage V_(SWN) at node 20 to increase to voltage level V_(SWN)_(—) _(HF). This causes inductor current I_(L18) to become lessnegative.

At time t₆, inductor current I_(L18) becomes zero causing switching nodevoltage V_(SWN) to oscillate about its nominal voltage V_(SWN) _(—)_(NOM) before settling to its nominal voltage.

After time t₆, signal V_(SWN) at node 20 and pulse width modulationsignal V_(PWM) causes flip-flops 210 and 212 to generate an incrementsignal that increments counter 214 and adjusts threshold voltage V_(TH)so that switching transistor 104 turns off or changes state later andpreferably when switching current I_(L18) has reached zero. In thisexample, although threshold voltage V_(TH) appearing at input terminal46 of ZCD comparator 24 has been decreased, it has not been decreasedsufficiently so that inductor current I_(L18) is zero or substantiallyzero when low side switching transistor 104 turns off. Thus, at time t₇,high side drive signal V_(HS) _(—) _(DRV) transitions from a logic lowvoltage level to a logic high voltage level while low side drive signalV_(LS) _(—) _(DRV) remains at a logic low voltage level. In response tohigh side drive signal V_(HS) _(—) _(DRV) transitioning to a logic highvoltage level and low side drive signal V_(LS) _(—) _(DRV) remaining ata logic low voltage level, voltage V_(SWN) at switching node 20transitions to a voltage level V_(SWN) _(—) _(HL), which is greater thanreference voltages V_(LSREF) and V_(HSREF) and close to the value ofinput voltage V_(IN). A positive inductor current I_(L18) flows fromnode 20 through inductor 18 and load 25.

At time t₈, driver circuit 16 generates a control signal that turns FET102 off and a control signal that leaves FET 104 off. In particular,gate voltage V_(HS) _(—) _(DRV) of switching transistor 102 transitionsto a logic low voltage level and gate voltage V_(LS) _(—) _(DRV) ofswitching transistor 104 remains at a logic low voltage level. Inresponse to the change in high side drive signal V_(HS) _(—) _(DRV) attime t₂, output voltage V_(OUT) decreases which results in switch nodevoltage V_(SWN) at node 20 decreasing to voltage level V_(SWN) _(—)_(LL) and inductor current I_(L18) beginning to decrease. Switch nodevoltage V_(SWN) is less than reference voltages V_(LSREF) and V_(LSREF),which leaves decrement signal V_(DEC) and increment signal V_(INC) thatare input into counter 214 and threshold voltage V_(TH) that appears atinput terminal 46 of comparator 24 unchanged.

At time t₉, low side drive signal V_(LS) _(—) _(DRV) transitions to alogic high voltage level turning on switching transistor 104, i.e.,closing the switch, which generates a drain-to-source on-voltage inswitching transistor 104 and causes switch node voltage V_(SWN) at node20 to increase to a voltage level V_(SWN) _(—) _(LH). Inductor currentI_(L18) continues to decrease.

At time t₁₀, high side drive signal V_(HS) _(—) _(DRV) remains at alogic low voltage level, low side drive signal _(VLS) _(—) _(DRV)remains at a logic high voltage level, and inductor current I_(L18)transitions to become a negative current.

At time t₁₁, high side drive signal V_(HS) _(—) _(DRV) remains at alogic low voltage level and low side drive signal V_(LS) _(—) _(DRV)transitions from a logic high voltage level to a logic low voltagelevel. Low side drive signal V_(LS) _(—) _(DRV) being at a logic lowvoltage level turns off switching transistor 104 which causes switchnode voltage V_(SWN) at node 20 to increase to voltage level V_(SWN)_(—) _(HL). This causes inductor current I_(L18) to become lessnegative, i.e., to increase.

At time t₁₂, inductor current I_(L18) becomes zero causing switchingnode voltage V_(SWN) to oscillate about its nominal voltage V_(SWN) _(—)_(NOM) before settling to its nominal voltage.

This process continues, i.e., using signals V_(SWN) and V_(PWM) togenerate counter increment signals, until threshold voltage V_(TH)appearing at input terminal 46 of comparator 24 is sufficiently loweredso that low side switching transistor 104 turns off when inductorcurrent I_(L18) reaches zero or substantially zero.

It should be noted that the operation has been described in usingsignals V_(SWN) and V_(PWM) to change, i.e., increase or decrease,threshold voltage V_(TH). However, a similar concept applies toembodiments such as those shown in FIGS. 1-3 in which signals V_(HS)_(—) _(DRV), VB_(HS) _(—) _(DRV), V_(LS) _(—) _(DRV), VB_(LS) _(—)_(DRV), V_(POR), V_(SFT) _(—) _(OK), and V_(NO) _(—) _(FAULT) are usedin place of pulse width modulation signal V_(PWM) to change thresholdvoltage V_(TH).

By now it should be appreciated that a power supply converter circuitand a method for adjusting its operation have been provided. Theconverter circuit monitors voltage signal V_(SWN) at node 20 or currentI_(L18) flowing from node 20 to determine whether the voltage or currentare positive, negative or zero. If voltage signal V_(SWN) or currentsignal I_(L18) are nonzero, threshold voltage V_(TH) appearing at inputterminal or node 46 of ZCD comparator 24 is adjusted up or down.Threshold voltage V_(TH) is adjusted up or increased if the voltageV_(SWN) is negative or current I_(L18) is positive and threshold voltageV_(TH) is adjusted down or decreased if voltage V_(SWN) is positive orcurrent I_(L18) is negative. Among other things, this improves theefficiency of the power supply converter circuit.

Although specific embodiments have been disclosed herein, it is notintended that the invention be limited to the disclosed embodiments.Those skilled in the art will recognize that modifications andvariations can be made without departing from the spirit of theinvention. For example, the switching network can be used with othertypes of converters such as, for example, boost converters, buck-boostconverters, etc. It is intended that the invention encompass all suchmodifications and variations as fall within the scope of the appendedclaims.

1. A power supply converter, comprising: a first switch having a controlterminal and first and second current conducting terminals; a secondswitch having a control terminal and first and second current conductingterminals, wherein the second terminal of the first switch is coupled tothe first terminal of the second switch to form a first node; a firstcomparator having first and second input terminals and an outputterminal, the first input terminal coupled for receiving a firstreference signal and the second input terminal coupled for receiving anadjustable threshold voltage, wherein the first comparator monitors acurrent flowing away from the first node and the first and secondswitches; and a control module having an input terminal and an outputterminal, the output terminal coupled to the first input terminal of thefirst comparator for transmitting the first reference signal.
 2. Thepower supply converter of claim 1, wherein the control module furthercomprises: a second comparator having first and second input terminalsand an output terminal, the first input terminal coupled to the firstnode and the second input terminal coupled for receiving a secondreference signal; and a third comparator having first and second inputterminals and an output terminal, the first input terminal coupled forreceiving a third reference signal and the second input terminal coupledto the first node.
 3. The power supply converter of claim 2, wherein thecontrol module further comprises: a first logic gate having a pluralityof input terminals and an output terminal, a first input terminal of theplurality of input terminals coupled to the output terminal of thesecond comparator; and a second logic gate having a plurality of inputterminals and an output terminal, a first input terminal of the secondlogic gate coupled to the output terminal of the third comparator. 4.The power supply converter of claim 3, wherein the first logic gateincludes second and third input terminals and the second logic gateincludes second and third input terminals, the second input terminals ofthe second and third logic gates coupled for receiving a first controlsignal and the third input terminals of the second and third logic gatescoupled for receiving a second control signal.
 5. The power supplyconverter of claim 4, wherein the control module further includes acounter having first and second input terminals, an output terminal, anda control terminal, the first input terminal of the counter coupled tothe output terminal of the second comparator and the second inputterminal of the counter coupled to the output terminal of the thirdcomparator.
 6. The power supply converter of claim 5, wherein thecontrol module further includes a latch having a data input terminal, aclock input terminal, a reset terminal, and an output terminal, theoutput terminal of the latch coupled to the second input terminal of thefirst comparator.
 7. The power supply converter of claim 6, wherein thecontrol module further includes a fourth logic gate having a pluralityof input terminals and an output terminal, the output terminal coupledto the clock input terminal of the latch.
 8. The power supply converterof claim 3, wherein the control module further comprises: a firstflip-flop having a clocking input terminal coupled to the outputterminal of the first logic gate; a second flip-flop having a clockinginput terminal coupled to the output terminal of the second logic gate;and wherein: the first logic gate includes second and third inputterminals and the second logic gate includes second and third inputterminals, the second input terminals of the second and third logicgates coupled for receiving a first control signal and the third inputterminal of the second logic gate coupled to the output terminal of thesecond flip-flop and the third input terminal of the third logic gatecoupled to the output terminal of the first flip-flop.
 9. The powersupply converter of claim 8, wherein the control module furthercomprises: a counter having an incrementing input terminal, adecrementing input terminal, and an output; and a Digital-to-AnalogConverter having an input coupled to the output of the counter and anoutput terminal coupled to the second input terminal of the firstcomparator.
 10. The power supply converter of claim 1, further includingan energy storage element coupled to the first node, wherein the currentflowing away from the first node and the first and second switches flowsthrough the energy storage element.
 11. A method for adjusting theoperation of a semiconductor component, comprising: changing anoperating state of a first semiconductor device having a currentconducting terminal coupled to a first node; monitoring a first signalat the first node; and adjusting a second signal at a second node if thefirst signal is a nonzero signal.
 12. The method of claim 11, whereinmonitoring the first signal at the first node includes determiningwhether a voltage at the first node is one of a positive voltage, anegative voltage, or a zero voltage.
 13. The method of claim 11, furtherincluding using the first signal at the first node to determine whethera current is positive or negative.
 14. The method of claim 11, whereinadjusting the second signal at the second node if the first signal is anonzero signal includes increasing the second signal if the first signalis less than zero.
 15. The method of claim 11, wherein adjusting thesecond signal at the second node if the first signal is a nonzero signalincludes decreasing the second signal if the first signal is a nonzerosignal.
 16. The method of claim 11, wherein adjusting the second signalat the second node if the first signal is nonzero includes one ofincreasing the second signal if the first signal is an inductor currentthat is positive or decreasing the second signal if the first signal isan inductor current that is negative.
 17. The method of claim 11,wherein monitoring the first signal at the first node includesmonitoring a switching voltage at the first node and wherein adjustingthe second signal at the second node if the first signal is a nonzerosignal includes adjusting a threshold voltage at the second node.
 18. Amethod for adjusting a threshold voltage, comprising: providing aswitching transistor having a control terminal and first and secondcurrent conducting terminals, the first current conducting terminalcoupled to an energy storage element; providing a first voltage at thecontrol terminal that turns off the switching transistor; determiningwhether a second voltage at the first current conducting terminal is anonzero voltage; and one of increasing a threshold voltage at a firstnode if the second voltage is less than zero or decreasing the thresholdvoltage at the first node if the second voltage is greater than zero.19. The method of claim 18, wherein determining whether the secondvoltage at the first current conducting terminal is a nonzero voltageincludes determining whether a current flowing through the energystorage elements is one of a positive current or a negative current bydetermining whether the second voltage at the first current conductingterminal is negative or positive.
 20. The method of claim 19, whereindetermining whether the second voltage at the first current conductingterminal is a nonzero voltage includes determining whether the switchingtransistor turns off before or after a current flowing through theenergy storage element is zero.